CD74HC573M, Защелка, 74HC573, Прозрачная D Типа, С Тремя Состояниями Неинвертирующий, 30 нс, 7.8 мА, SOIC

The CD74HC573M is an octal CMOS Transparent D Latch with 3-state outputs. This high speed latch is designed for 2 to 6V VCC operation. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered OE input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor.

• Balanced propagation delays and transition times
• Bus driver outputs drive up to 15 LS-TTL loads
• Significant power reduction compared to LS-TTL logic ICs
• Green product and no Sb/Br

Полупроводники — МикросхемыЛогикаТриггеры-защелки

Технические параметры