SN74LVTH373PW, Защелка, семейство LVT, 74LVT373, Прозрачная, С Тремя Состояниями, 2.6 нс, 64 мА, TSSOP

The SN74LVTH373PW is an octal transparent D Latch with 3-state outputs. It is designed specifically for low-voltage VCC operation, but with the capability to provide a TTL interface to a 5V system environment. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered OE input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pull-up components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

• Support unregulated battery operation down to 2.7V
• Ioff and power-up 3-state support hot insertion
• Bus hold on data inputs eliminates the need for external pull-up/pull-down resistors
• Latch-up performance exceeds 500mA per JESD 17
• Green product and no Sb/Br

Полупроводники — МикросхемыЛогикаТриггеры-защелки

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