SN74ALS165D, Регистр сдвига, семейство ALS, 74ALS165

The SN74ALS165D is a 8-bit parallel-load serial Shift Register that, when clocked, shift the data toward serial (QH and QH) outputs. parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The ALS165 have a clock-inhibit function and complemented serial outputs. clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and the clock inhibit (CLK INH) input is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. parallel loading is inhibited when SH/LD is held high. The parallel inputs to the register are enabled while SH/LD is low independently of the levels of the CLK, CLK INH or serial (SER) inputs.

• Complementary outputs
• Direct overriding load (data) inputs
• Gated clock inputs
• Parallel-to-serial data conversion
• Green product and no Sb/Br

Полупроводники — МикросхемыЛогикаСдвигающие Регистры

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