CD74HC390E, Декадный счетчик со сквозным переносом, семейство HC, 35МГц, 2В — 6В, DIP-16

The CD74HC390E is a high speed CMOS dual decade Ripple Counter pin compatible with low-power Schottky TTL (LSTTL). It is divided into four separately clocked sections. The counter has two divide-by-2 sections and two divide-by-5 sections. These sections are normally used in a BCD decade or bi quinary configuration, since they share a common master reset (nMR). If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCP0 and nCP1) of each section allow ripple counter or frequency division applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100. Each section is triggered by the high-to-low transition of the input pulses (nCP0 and nCP1). For BCD decade operation, the nQ0 output is connected to the nCP1 input of the divide-by-5 section.

• Two master reset inputs to clear each decade counter individually
• Balanced propagation delay and transition times
• Significant power reduction compared to LSTTL logic ICs
• High noise immunity
• Direct LSTTL input logic compatibility
• CMOS Input compatibility

Полупроводники — МикросхемыЛогикаСчетчики

Технические параметры