SN74AUP2G79DCUR, Триггер, 74AUP79, D, 4.1 нс, 260 МГц, 4 мА, VSSOP

The SN74AUP2G79DCUR is a dual positive-edge-triggered D-type Flip-flop fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 to 3.6V, resulting in increased battery life. This product also maintains excellent signal integrity. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

• Suitable for point-to-point applications
• Ioff Supports partial-power-down mode operation
• 0.9µA Maximum low static-power consumption
• 3pF Typical at 3.3V low dynamic-power consumption
• 1.5pF Typical low input capacitance
• Low noise — Overshoot and undershoot &lt,10% of VCC
• Green product and no Sb/Br

Полупроводники — МикросхемыЛогикаТриггеры

Технические параметры