74LV164D,112, Регистр сдвига, семейство LV, высокоскоростная КМОП, 74LV164, Последовательный в Параллельный

The 74LV164D is a 8-bit CMOS serial-in/parallel-out Shift Register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB) and either input can be used as an active high enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied high. Data shifts one place to the right on each low-to-high transition of the clock input (CP) and enters into Q0, which is the logical AND-function of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge. A low on the master reset input (MR) overrides all other inputs and clears the register asynchronously, forcing all outputs low. It is pin and function compatible with the 74HC164 and 74HCT164.

• Gated serial data inputs
• Asynchronous master reset
• Optimized for low-voltage applications

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